Computer-enabled creation of designs is used in a wide variety of different applications and industries to allow the design of products to be more efficient and economical. One common application is electronic design automation (EDA), in which the designs for electronic components such as integrated circuits, circuit boards, and other components are created, viewed, and edited using graphical software applications implemented by computer systems. Such circuit design can include schematic or symbolic designs, physical layout designs, and other types of designs including components, electrical interconnects, power sources, etc. In some cases, designs are organized into “Intellectual Property (IP) cores,” which are standardized packaged designs for products which can be exported to or imported from other organizations or entities and used as the foundation and changed as necessary to create similar designs and products or use the design in a different context. To produce such IP cores and designs more quickly and efficiently, organizations may use design flows, which are standardized procedures and rules which all stages of the design must follow to maintain consistency and reduce inefficiency and errors in the design process.
EDA designs typically reference libraries of data that describe designs and standardized components of designs. This data can include cells, which are descriptions of designs or components of designs. For example, a cell can be a block having inputs and/or outputs and which can be used with other cells to create a more complex design. The library data can also include cellviews, which are one or views associated with each cell, each cellview having a particular format in which to view its associated cell, such as a schematic view, physical layout view, text description view (such as VHDL or Verilog HDL), etc. Design and reference libraries typically include hundreds to thousands of cells and each cell may have several cellviews.
As part of an IP core export or import strategy to produce a fully functional core design, ensuring that all cellviews and other data in referenced libraries are correct and compatible with one or more design flows can be very time consuming due to a combination of complexity and quantity. Fixing libraries and adding additional tool/flow support can also be very resource intensive.
For example, the fundamental verification of a design, including correctness and compatibility checks, that needs to be performed before finalizing (e.g., “releasing” or “qualifying”) a design or IP core library includes several different tasks. One example is verifying that all cellviews are up to date, e.g., a layout view is not older than a schematic view. Another example is verifying that data across all cellviews are consistent, e.g., the same pin names are present across all views. An additional task is to verify that data meets desired quality metrics, such as using design rule check (DRC) software to determine whether the physical layout of a particular design layout satisfies recommended design rules and parameters, using Layout Versus Schematic (LVS) verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design, or checking whether electronic constraints are met. In another example task for verification, easily automated tasks can be repeated, such as testing scripts providing automated functions or physical and design verification. Another example includes enforcing company-mandated data and flow standards, such as naming conventions. Also, fundamental database format integrity checks can be performed, such as a scan using oaScan, an application from Cadence Design Systems, Inc. that scans the contents of a library and checks for and repairs inconsistencies or data corruption in databases. In addition, metrics can be gathered, such as individual cell utilization, areas, device usage, etc., which may be desired for an importer of an IP core design, for example.
Despite the need for such thorough verification procedures of database libraries used for designs, design teams tend to run only a subset of the required number of tests and verification procedures, and do so in an ad-hoc manner. For example, many of the above verification tests are only run interactively or manually, and not in a fully automated manner. Exhaustive testing is not generally performed due to lack of an appropriately comprehensive and configurable system to enable such testing. This lack of systematic and comprehensive verification leads to subsequent integration issues and recalls of manufactured products. For example, integration failures can result in delayed tapeouts of integrated circuits and create additional inefficiencies in having to re-address the underlying errors or other issues in the design.